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| int(* | access_memory )(struct target *target, const struct riscv_mem_access_args args) |
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| int(* | authdata_read )(struct target *target, uint32_t *value, unsigned int index) |
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| int(* | authdata_write )(struct target *target, uint32_t value, unsigned int index) |
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| bool | autofence |
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| struct command_context * | cmd_ctx |
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| unsigned int | common_magic |
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| struct reg_name_table | custom_register_names |
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| unsigned int(* | data_bits )(struct target *target) |
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| int(* | dmi_read )(struct target *target, uint32_t *value, uint32_t address) |
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| int(* | dmi_write )(struct target *target, uint32_t address, uint32_t value) |
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| unsigned int | dtm_version |
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| int(* | execute_progbuf )(struct target *target, uint32_t *cmderr) |
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| struct list_head | expose_csr |
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| struct list_head | expose_custom |
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| void(* | fill_dm_nop )(const struct target *target, uint8_t *buf) |
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| void(* | fill_dmi_read )(const struct target *target, uint8_t *buf, uint32_t a) |
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| void(* | fill_dmi_write )(const struct target *target, uint8_t *buf, uint32_t a, uint32_t d) |
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| uint32_t(* | get_dmi_address )(const struct target *target, uint32_t dm_address) |
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| unsigned int(* | get_dmi_address_bits )(const struct target *target) |
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| int(* | get_hart_state )(struct target *target, enum riscv_hart_state *state) |
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| bool(* | get_impebreak )(const struct target *target) |
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| unsigned int(* | get_progbufsize )(const struct target *target) |
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| int(* | halt_go )(struct target *target) |
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| unsigned int | halt_group_repoll_count |
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| int(* | halt_prep )(struct target *target) |
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| enum riscv_halt_reason(* | halt_reason )(struct target *target) |
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| enum target_event | halted_callback_event |
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| bool | halted_needs_event_callback |
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| int(* | handle_became_halted )(struct target *target, enum riscv_hart_state previous_riscv_state) |
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| int(* | handle_became_running )(struct target *target, enum riscv_hart_state previous_riscv_state) |
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| int(* | handle_became_unavailable )(struct target *target, enum riscv_hart_state previous_riscv_state) |
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| struct list_head | hide_csr |
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| int(* | invalidate_cached_progbuf )(struct target *target) |
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| enum riscv_isrmasking_mode | isrmask_mode |
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| int64_t | last_activity |
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| enum riscv_mem_access_method | mem_access_methods [RISCV_MEM_ACCESS_MAX_METHODS_NUM] |
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| bool | mem_access_warn [RISCV_MEM_ACCESS_MAX_METHODS_NUM] |
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| riscv_reg_t | misa |
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| bool | need_single_step |
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| unsigned int | num_enabled_mem_access_methods |
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| int(* | on_step )(struct target *target) |
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| bool | prepped |
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| bool | range_trigger_fallback_encountered |
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| riscv_insn_t(* | read_progbuf )(struct target *target, unsigned int index) |
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| char ** | reg_names |
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| bool * | reserved_triggers |
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| int | reset_delays_wait |
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| int(* | resume_go )(struct target *target) |
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| int(* | resume_prep )(struct target *target) |
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| struct riscv_sample_buf | sample_buf |
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| riscv_sample_config_t | sample_config |
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| int(* | sample_memory )(struct target *target, struct riscv_sample_buf *buf, riscv_sample_config_t *config, int64_t until_ms) |
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| int(* | select_target )(struct target *target) |
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| bool | selected |
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| riscv_reg_info_t | shared_reg_info |
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| int(* | step_current_hart )(struct target *target) |
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| int(* | tick )(struct target *target) |
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| int | tinfo_version |
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| unsigned int | trigger_count |
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| int64_t | trigger_hit |
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| unsigned int | trigger_tinfo [RISCV_MAX_TRIGGERS] |
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| int64_t | trigger_unique_id [RISCV_MAX_HWBPS] |
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| bool | triggers_enumerated |
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| struct reg_data_type | type_uint128_vector |
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| struct reg_data_type | type_uint16_vector |
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| struct reg_data_type | type_uint32_vector |
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| struct reg_data_type | type_uint64_vector |
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| struct reg_data_type | type_uint8_vector |
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| struct reg_data_type | type_vector |
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| struct reg_data_type_union_field | vector_fields [5] |
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| struct reg_data_type_vector | vector_uint128 |
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| struct reg_data_type_vector | vector_uint16 |
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| struct reg_data_type_vector | vector_uint32 |
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| struct reg_data_type_vector | vector_uint64 |
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| struct reg_data_type_vector | vector_uint8 |
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| struct reg_data_type_union | vector_union |
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| void * | version_specific |
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| enum riscv_virt2phys_mode | virt2phys_mode |
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| unsigned int | vlenb |
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| enum yes_no_maybe | vsew64_supported |
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| bool | wp_allow_equality_match_trigger |
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| bool | wp_allow_ge_lt_trigger |
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| bool | wp_allow_napot_trigger |
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| struct list_head * | wp_triggers_negative_cache |
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| int(* | write_progbuf )(struct target *target, unsigned int index, riscv_insn_t d) |
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| int | xlen |
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Definition at line 168 of file riscv.h.
