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Data Structures | |
| struct | bits_t |
| struct | memory_cache_line |
| struct | riscv011_info_t |
| struct | scans_t |
Macros | |
| #define | CACHE_NO_READ 128 |
| Write cache to the target, and optionally run the program. More... | |
| #define | CSR_BPCONTROL_BPACTION (0xff<<11) |
| #define | CSR_BPCONTROL_BPMATCH (0xf<<7) |
| #define | CSR_BPCONTROL_H (1<<5) |
| #define | CSR_BPCONTROL_M (1<<6) |
| #define | CSR_BPCONTROL_R (1<<2) |
| #define | CSR_BPCONTROL_S (1<<4) |
| #define | CSR_BPCONTROL_U (1<<3) |
| #define | CSR_BPCONTROL_W (1<<1) |
| #define | CSR_BPCONTROL_X (1<<0) |
| #define | DBUS 0x11 |
| #define | DBUS_ADDRESS_START 36 |
| #define | DBUS_ADDRESS_UNKNOWN 0xffff |
| #define | DBUS_DATA_SIZE 34 |
| #define | DBUS_DATA_START 2 |
| #define | DBUS_OP_SIZE 2 |
| #define | DBUS_OP_START 0 |
| #define | DEBUG_LENGTH 264 |
| #define | DEBUG_RAM_START 0x400 |
| #define | DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8) |
| #define | DEBUG_ROM_RESUME (DEBUG_ROM_START + 4) |
| #define | DEBUG_ROM_START 0x800 |
| #define | DMAUTHDATA0 0x12 |
| #define | DMAUTHDATA1 0x13 |
| #define | DMCONTROL 0x10 |
| #define | DMCONTROL_ACCESS (7<<12) |
| #define | DMCONTROL_AUTOINCREMENT (1<<15) |
| #define | DMCONTROL_BUSERROR (7<<19) |
| #define | DMCONTROL_FULLRESET 1 |
| #define | DMCONTROL_HALTNOT (((uint64_t)1)<<32) |
| #define | DMCONTROL_HARTID (0x3ff<<2) |
| #define | DMCONTROL_INTERRUPT (((uint64_t)1)<<33) |
| #define | DMCONTROL_NDRESET (1<<1) |
| #define | DMCONTROL_SERIAL (3<<16) |
| #define | DMINFO 0x11 |
| #define | DMINFO_ABUSSIZE (0x7fU<<25) |
| #define | DMINFO_ACCESS128 (1<<20) |
| #define | DMINFO_ACCESS16 (1<<17) |
| #define | DMINFO_ACCESS32 (1<<18) |
| #define | DMINFO_ACCESS64 (1<<19) |
| #define | DMINFO_ACCESS8 (1<<16) |
| #define | DMINFO_AUTHBUSY (1<<4) |
| #define | DMINFO_AUTHENTICATED (1<<5) |
| #define | DMINFO_AUTHTYPE (3<<2) |
| #define | DMINFO_DRAMSIZE (0x3f<<10) |
| #define | DMINFO_SERIALCOUNT (0xf<<21) |
| #define | DMINFO_VERSION 3 |
| #define | DRAM_CACHE_SIZE 16 |
| #define | DTMCONTROL 0x10 |
| #define | DTMCONTROL_ADDRBITS (0xf<<4) |
| #define | DTMCONTROL_DBUS_RESET (1<<16) |
| #define | DTMCONTROL_IDLE (7<<10) |
| #define | DTMCONTROL_VERSION (0xf) |
| #define | SETHALTNOT 0x10c |
Typedefs | |
| typedef enum slot | slot_t |
Enumerations | |
| enum | dbus_op_t { DBUS_OP_NOP = 0 , DBUS_OP_READ = 1 , DBUS_OP_WRITE = 2 } |
| enum | dbus_status_t { DBUS_STATUS_SUCCESS = 0 , DBUS_STATUS_FAILED = 2 , DBUS_STATUS_BUSY = 3 } |
| enum | riscv_error_t { RE_OK , RE_FAIL , RE_AGAIN } |
| enum | slot { SLOT0 , SLOT1 , SLOT_LAST } |
Functions | |
| static int | access_memory (struct target *target, const struct riscv_mem_access_args args) |
| static void | add_dbus_scan (const struct target *target, struct scan_field *field, uint8_t *out_value, uint8_t *in_value, dbus_op_t op, uint16_t address, uint64_t data) |
| static int | arch_state (struct target *target) |
| static int | assert_reset (struct target *target) |
| static int | cache_check (struct target *target) |
| static void | cache_clean (struct target *target) |
| static uint64_t | cache_get (struct target *target, slot_t slot) |
| static uint32_t | cache_get32 (struct target *target, unsigned int address) |
| static void | cache_invalidate (struct target *target) |
| static void | cache_set (struct target *target, slot_t slot, uint64_t data) |
| static void | cache_set32 (struct target *target, unsigned int index, uint32_t data) |
| static void | cache_set_jump (struct target *target, unsigned int index) |
| static void | cache_set_load (struct target *target, unsigned int index, unsigned int reg, slot_t slot) |
| static void | cache_set_store (struct target *target, unsigned int index, unsigned int reg, slot_t slot) |
| static int | cache_write (struct target *target, unsigned int address, bool run) |
| static | COMMAND_HELPER (riscv011_print_info, struct target *target) |
| static uint64_t | dbus_read (struct target *target, uint16_t address) |
| static dbus_status_t | dbus_scan (struct target *target, uint16_t *address_in, uint64_t *data_in, dbus_op_t op, uint16_t address_out, uint64_t data_out) |
| static void | dbus_write (struct target *target, uint16_t address, uint64_t value) |
| static int | deassert_reset (struct target *target) |
| static void | deinit_target (struct target *target) |
| static uint16_t | dram_address (unsigned int index) |
| static int | dram_check32 (struct target *target, unsigned int index, uint32_t expected) |
| static uint32_t | dram_read32 (struct target *target, unsigned int index) |
| static void | dram_write32 (struct target *target, unsigned int index, uint32_t value, bool set_interrupt) |
| static void | dram_write_jump (struct target *target, unsigned int index, bool set_interrupt) |
| static void | dump_debug_ram (struct target *target) |
| static void | dump_field (const struct scan_field *field) |
| static int | examine (struct target *target) |
| static int | execute_resume (struct target *target, bool step) |
| static int | full_step (struct target *target, bool announce) |
| static riscv011_info_t * | get_info (const struct target *target) |
| static int | halt (struct target *target) |
| static int | handle_halt (struct target *target, bool announce) |
| Since almost everything can be accomplish by scanning the dbus register, all functions here assume dbus is already selected. More... | |
| static riscv_error_t | handle_halt_routine (struct target *target) |
| static uint32_t | idcode_scan (struct target *target) |
| static void | increase_dbus_busy_delay (struct target *target) |
| static void | increase_interrupt_high_delay (struct target *target) |
| static int | init_target (struct command_context *cmd_ctx, struct target *target) |
| static uint32_t | load (const struct target *target, unsigned int rd, unsigned int base, int16_t offset) |
| static uint32_t | load_slot (const struct target *target, unsigned int dest, slot_t slot) |
| static int | maybe_read_tselect (struct target *target) |
| static int | maybe_write_tselect (struct target *target) |
| static int | poll_target (struct target *target, bool announce) |
| static int | read_bits (struct target *target, bits_t *result) |
| Read the haltnot and interrupt bits. More... | |
| static int | read_memory (struct target *target, const struct riscv_mem_access_args args) |
| static int | read_remote_csr (struct target *target, uint64_t *value, uint32_t csr) |
| static uint64_t | reg_cache_get (struct target *target, unsigned int number) |
| static void | reg_cache_set (struct target *target, unsigned int number, uint64_t value) |
| static int | register_read (struct target *target, riscv_reg_t *value, int regnum) |
| static int | register_write (struct target *target, unsigned int number, uint64_t value) |
| static int | riscv011_authdata_read (struct target *target, uint32_t *value, unsigned int index) |
| static int | riscv011_authdata_write (struct target *target, uint32_t value, unsigned int index) |
| static bool | riscv011_get_impebreak (const struct target *target) |
| static unsigned int | riscv011_get_progbufsize (const struct target *target) |
| int | riscv011_get_register (struct target *target, riscv_reg_t *value, enum gdb_regno regid) |
| static int | riscv011_poll (struct target *target) |
| static int | riscv011_resume (struct target *target, bool current, target_addr_t address, bool handle_breakpoints, bool debug_execution) |
| int | riscv011_set_register (struct target *target, enum gdb_regno regid, riscv_reg_t value) |
| static void | scans_add_read (scans_t *scans, slot_t slot, bool set_interrupt) |
| Add one or more scans to read the indicated slot. More... | |
| static void | scans_add_read32 (scans_t *scans, uint16_t address, bool set_interrupt) |
| Add a 32-bit dbus read. More... | |
| static void | scans_add_write32 (scans_t *scans, uint16_t address, uint32_t data, bool set_interrupt) |
| Add a 32-bit dbus write to the scans structure. More... | |
| static void | scans_add_write_jump (scans_t *scans, uint16_t address, bool set_interrupt) |
| Add a 32-bit dbus write for an instruction that jumps to the beginning of debug RAM. More... | |
| static void | scans_add_write_load (scans_t *scans, uint16_t address, unsigned int reg, slot_t slot, bool set_interrupt) |
| Add a 32-bit dbus write for an instruction that loads from the indicated slot. More... | |
| static void | scans_add_write_store (scans_t *scans, uint16_t address, unsigned int reg, slot_t slot, bool set_interrupt) |
| Add a 32-bit dbus write for an instruction that stores to the indicated slot. More... | |
| static scans_t * | scans_delete (scans_t *scans) |
| static void | scans_dump (scans_t *scans) |
| static int | scans_execute (scans_t *scans) |
| static uint32_t | scans_get_u32 (scans_t *scans, unsigned int index, unsigned int first, unsigned int num) |
| static uint64_t | scans_get_u64 (scans_t *scans, unsigned int index, unsigned int first, unsigned int num) |
| static scans_t * | scans_new (struct target *target, unsigned int scan_count) |
| static void | scans_reset (scans_t *scans) |
| static uint64_t | set_ebreakx_fields (uint64_t dcsr, const struct target *target) |
| static int | setup_write_memory (struct target *target, uint32_t size) |
| static unsigned int | slot_offset (const struct target *target, slot_t slot) |
| static int | step (struct target *target, bool current, target_addr_t address, bool handle_breakpoints) |
| static uint32_t | store (const struct target *target, unsigned int src, unsigned int base, int16_t offset) |
| static uint32_t | store_slot (const struct target *target, unsigned int src, slot_t slot) |
| static int | strict_step (struct target *target, bool announce) |
| static int | update_mstatus_actual (struct target *target) |
| static int | wait_for_authbusy (struct target *target) |
| static int | wait_for_debugint_clear (struct target *target, bool ignore_first) |
| static int | wait_for_state (struct target *target, enum target_state state) |
| static int | write_gpr (struct target *target, unsigned int gpr, uint64_t value) |
| static int | write_memory (struct target *target, const struct riscv_mem_access_args args) |
| static int | write_remote_csr (struct target *target, uint32_t csr, uint64_t value) |
Variables | |
| struct target_type | riscv011_target |
Macro Definition Documentation
◆ CACHE_NO_READ
| #define CACHE_NO_READ 128 |
Write cache to the target, and optionally run the program.
Then read the value at address into the cache, assuming address < 128.
Definition at line 864 of file riscv-011.c.
◆ CSR_BPCONTROL_BPACTION
| #define CSR_BPCONTROL_BPACTION (0xff<<11) |
Definition at line 85 of file riscv-011.c.
◆ CSR_BPCONTROL_BPMATCH
| #define CSR_BPCONTROL_BPMATCH (0xf<<7) |
Definition at line 84 of file riscv-011.c.
◆ CSR_BPCONTROL_H
| #define CSR_BPCONTROL_H (1<<5) |
Definition at line 82 of file riscv-011.c.
◆ CSR_BPCONTROL_M
| #define CSR_BPCONTROL_M (1<<6) |
Definition at line 83 of file riscv-011.c.
◆ CSR_BPCONTROL_R
| #define CSR_BPCONTROL_R (1<<2) |
Definition at line 79 of file riscv-011.c.
◆ CSR_BPCONTROL_S
| #define CSR_BPCONTROL_S (1<<4) |
Definition at line 81 of file riscv-011.c.
◆ CSR_BPCONTROL_U
| #define CSR_BPCONTROL_U (1<<3) |
Definition at line 80 of file riscv-011.c.
◆ CSR_BPCONTROL_W
| #define CSR_BPCONTROL_W (1<<1) |
Definition at line 78 of file riscv-011.c.
◆ CSR_BPCONTROL_X
| #define CSR_BPCONTROL_X (1<<0) |
Definition at line 77 of file riscv-011.c.
◆ DBUS
| #define DBUS 0x11 |
Definition at line 102 of file riscv-011.c.
◆ DBUS_ADDRESS_START
| #define DBUS_ADDRESS_START 36 |
Definition at line 117 of file riscv-011.c.
◆ DBUS_ADDRESS_UNKNOWN
| #define DBUS_ADDRESS_UNKNOWN 0xffff |
Definition at line 163 of file riscv-011.c.
◆ DBUS_DATA_SIZE
| #define DBUS_DATA_SIZE 34 |
Definition at line 116 of file riscv-011.c.
◆ DBUS_DATA_START
| #define DBUS_DATA_START 2 |
Definition at line 115 of file riscv-011.c.
◆ DBUS_OP_SIZE
| #define DBUS_OP_SIZE 2 |
Definition at line 104 of file riscv-011.c.
◆ DBUS_OP_START
| #define DBUS_OP_START 0 |
Definition at line 103 of file riscv-011.c.
◆ DEBUG_LENGTH
| #define DEBUG_LENGTH 264 |
Definition at line 219 of file riscv-011.c.
◆ DEBUG_RAM_START
| #define DEBUG_RAM_START 0x400 |
Definition at line 90 of file riscv-011.c.
◆ DEBUG_ROM_EXCEPTION
| #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8) |
Definition at line 89 of file riscv-011.c.
◆ DEBUG_ROM_RESUME
| #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4) |
Definition at line 88 of file riscv-011.c.
◆ DEBUG_ROM_START
| #define DEBUG_ROM_START 0x800 |
Definition at line 87 of file riscv-011.c.
◆ DMAUTHDATA0
| #define DMAUTHDATA0 0x12 |
Definition at line 158 of file riscv-011.c.
◆ DMAUTHDATA1
| #define DMAUTHDATA1 0x13 |
Definition at line 159 of file riscv-011.c.
◆ DMCONTROL
| #define DMCONTROL 0x10 |
Definition at line 133 of file riscv-011.c.
◆ DMCONTROL_ACCESS
| #define DMCONTROL_ACCESS (7<<12) |
Definition at line 139 of file riscv-011.c.
◆ DMCONTROL_AUTOINCREMENT
| #define DMCONTROL_AUTOINCREMENT (1<<15) |
Definition at line 138 of file riscv-011.c.
◆ DMCONTROL_BUSERROR
| #define DMCONTROL_BUSERROR (7<<19) |
Definition at line 136 of file riscv-011.c.
◆ DMCONTROL_FULLRESET
| #define DMCONTROL_FULLRESET 1 |
Definition at line 142 of file riscv-011.c.
◆ DMCONTROL_HALTNOT
| #define DMCONTROL_HALTNOT (((uint64_t)1)<<32) |
Definition at line 135 of file riscv-011.c.
◆ DMCONTROL_HARTID
| #define DMCONTROL_HARTID (0x3ff<<2) |
Definition at line 140 of file riscv-011.c.
◆ DMCONTROL_INTERRUPT
| #define DMCONTROL_INTERRUPT (((uint64_t)1)<<33) |
Definition at line 134 of file riscv-011.c.
◆ DMCONTROL_NDRESET
| #define DMCONTROL_NDRESET (1<<1) |
Definition at line 141 of file riscv-011.c.
◆ DMCONTROL_SERIAL
| #define DMCONTROL_SERIAL (3<<16) |
Definition at line 137 of file riscv-011.c.
◆ DMINFO
| #define DMINFO 0x11 |
Definition at line 144 of file riscv-011.c.
◆ DMINFO_ABUSSIZE
| #define DMINFO_ABUSSIZE (0x7fU<<25) |
Definition at line 145 of file riscv-011.c.
◆ DMINFO_ACCESS128
| #define DMINFO_ACCESS128 (1<<20) |
Definition at line 147 of file riscv-011.c.
◆ DMINFO_ACCESS16
| #define DMINFO_ACCESS16 (1<<17) |
Definition at line 150 of file riscv-011.c.
◆ DMINFO_ACCESS32
| #define DMINFO_ACCESS32 (1<<18) |
Definition at line 149 of file riscv-011.c.
◆ DMINFO_ACCESS64
| #define DMINFO_ACCESS64 (1<<19) |
Definition at line 148 of file riscv-011.c.
◆ DMINFO_ACCESS8
| #define DMINFO_ACCESS8 (1<<16) |
Definition at line 151 of file riscv-011.c.
◆ DMINFO_AUTHBUSY
| #define DMINFO_AUTHBUSY (1<<4) |
Definition at line 154 of file riscv-011.c.
◆ DMINFO_AUTHENTICATED
| #define DMINFO_AUTHENTICATED (1<<5) |
Definition at line 153 of file riscv-011.c.
◆ DMINFO_AUTHTYPE
| #define DMINFO_AUTHTYPE (3<<2) |
Definition at line 155 of file riscv-011.c.
◆ DMINFO_DRAMSIZE
| #define DMINFO_DRAMSIZE (0x3f<<10) |
Definition at line 152 of file riscv-011.c.
◆ DMINFO_SERIALCOUNT
| #define DMINFO_SERIALCOUNT (0xf<<21) |
Definition at line 146 of file riscv-011.c.
◆ DMINFO_VERSION
| #define DMINFO_VERSION 3 |
Definition at line 156 of file riscv-011.c.
◆ DRAM_CACHE_SIZE
| #define DRAM_CACHE_SIZE 16 |
Definition at line 165 of file riscv-011.c.
◆ DTMCONTROL
| #define DTMCONTROL 0x10 |
Definition at line 96 of file riscv-011.c.
◆ DTMCONTROL_ADDRBITS
| #define DTMCONTROL_ADDRBITS (0xf<<4) |
Definition at line 99 of file riscv-011.c.
◆ DTMCONTROL_DBUS_RESET
| #define DTMCONTROL_DBUS_RESET (1<<16) |
Definition at line 97 of file riscv-011.c.
◆ DTMCONTROL_IDLE
| #define DTMCONTROL_IDLE (7<<10) |
Definition at line 98 of file riscv-011.c.
◆ DTMCONTROL_VERSION
| #define DTMCONTROL_VERSION (0xf) |
Definition at line 100 of file riscv-011.c.
◆ SETHALTNOT
| #define SETHALTNOT 0x10c |
Definition at line 92 of file riscv-011.c.
Typedef Documentation
◆ slot_t
Enumeration Type Documentation
◆ dbus_op_t
| enum dbus_op_t |
| Enumerator | |
|---|---|
| DBUS_OP_NOP | |
| DBUS_OP_READ | |
| DBUS_OP_WRITE | |
Definition at line 105 of file riscv-011.c.
◆ dbus_status_t
| enum dbus_status_t |
| Enumerator | |
|---|---|
| DBUS_STATUS_SUCCESS | |
| DBUS_STATUS_FAILED | |
| DBUS_STATUS_BUSY | |
Definition at line 110 of file riscv-011.c.
◆ riscv_error_t
| enum riscv_error_t |
| Enumerator | |
|---|---|
| RE_OK | |
| RE_FAIL | |
| RE_AGAIN | |
Definition at line 119 of file riscv-011.c.
◆ slot
| enum slot |
| Enumerator | |
|---|---|
| SLOT0 | |
| SLOT1 | |
| SLOT_LAST | |
Definition at line 125 of file riscv-011.c.
Function Documentation
◆ access_memory()
|
static |
Definition at line 2341 of file riscv-011.c.
References read_memory(), riscv_mem_access_is_valid(), riscv_mem_access_is_write(), and write_memory().
Referenced by init_target().
◆ add_dbus_scan()
|
static |
Definition at line 356 of file riscv-011.c.
References address, buf_set_u64(), DBUS_ADDRESS_START, DBUS_DATA_SIZE, DBUS_DATA_START, DBUS_OP_SIZE, DBUS_OP_START, DMCONTROL_INTERRUPT, get_info(), scan_field::in_value, info, jtag_add_dr_scan(), jtag_add_runtest(), scan_field::num_bits, op, scan_field::out_value, RISCV_INFO, target::tap, and TAP_IDLE.
Referenced by scans_add_read32(), and scans_add_write32().
◆ arch_state()
|
static |
Definition at line 2350 of file riscv-011.c.
References ERROR_OK.
◆ assert_reset()
|
static |
Definition at line 1973 of file riscv-011.c.
References cache_invalidate(), CSR_DCSR, csrw(), DCSR_FULLRESET, DCSR_HALT, DCSR_NDRESET, DEBUG_RAM_START, dram_write32(), dram_write_jump(), ERROR_FAIL, ERROR_OK, get_info(), info, jtag_add_ir_scan(), LOG_ERROR, lw(), target::reset_halt, S0, select_dbus, set_ebreakx_fields(), target::state, target::tap, TAP_IDLE, TARGET_RESET, wait_for_debugint_clear(), and ZERO.
◆ cache_check()
|
static |
Definition at line 842 of file riscv-011.c.
References dram_check32(), dump_debug_ram(), ERROR_FAIL, ERROR_OK, get_info(), and info.
Referenced by examine().
◆ cache_clean()
|
static |
Definition at line 832 of file riscv-011.c.
References get_info(), and info.
Referenced by cache_write(), read_memory(), and write_memory().
◆ cache_get()
Definition at line 1004 of file riscv-011.c.
References cache_get32(), offset, riscv_xlen(), and slot_offset().
Referenced by read_remote_csr(), register_read(), and write_memory().
◆ cache_get32()
|
static |
Definition at line 994 of file riscv-011.c.
References address, dram_read32(), get_info(), and info.
Referenced by cache_get(), examine(), read_remote_csr(), register_read(), and register_write().
◆ cache_invalidate()
|
static |
Definition at line 821 of file riscv-011.c.
References get_info(), and info.
Referenced by assert_reset(), examine(), execute_resume(), and handle_halt_routine().
◆ cache_set()
Definition at line 781 of file riscv-011.c.
References cache_set32(), offset, riscv_xlen(), and slot_offset().
Referenced by execute_resume(), register_write(), riscv011_get_register(), write_gpr(), write_memory(), and write_remote_csr().
◆ cache_set32()
|
static |
Definition at line 766 of file riscv-011.c.
References get_info(), info, and LOG_DEBUG.
Referenced by cache_set(), cache_set_jump(), cache_set_load(), cache_set_store(), examine(), execute_resume(), halt(), read_memory(), read_remote_csr(), register_read(), register_write(), riscv011_get_register(), setup_write_memory(), and write_remote_csr().
◆ cache_set_jump()
|
static |
Definition at line 789 of file riscv-011.c.
References cache_set32(), DEBUG_RAM_START, DEBUG_ROM_RESUME, jal(), and MAX_INT21.
Referenced by examine(), execute_resume(), halt(), read_memory(), read_remote_csr(), register_read(), register_write(), riscv011_get_register(), setup_write_memory(), write_gpr(), write_memory(), and write_remote_csr().
◆ cache_set_load()
|
static |
Definition at line 796 of file riscv-011.c.
References cache_set32(), DEBUG_RAM_START, load(), MAX_INT12, offset, slot_offset(), and ZERO.
Referenced by execute_resume(), register_write(), riscv011_get_register(), write_gpr(), write_memory(), and write_remote_csr().
◆ cache_set_store()
|
static |
Definition at line 804 of file riscv-011.c.
References cache_set32(), DEBUG_RAM_START, MAX_INT12, offset, slot_offset(), store(), and ZERO.
Referenced by read_remote_csr(), register_read(), register_write(), and write_memory().
◆ cache_write()
|
static |
Definition at line 865 of file riscv-011.c.
References address, cache_clean(), CACHE_NO_READ, DBUS_ADDRESS_START, DBUS_DATA_START, DBUS_OP_SIZE, DBUS_OP_START, DBUS_STATUS_BUSY, DBUS_STATUS_FAILED, DBUS_STATUS_SUCCESS, dbus_write(), DMCONTROL, DMCONTROL_HALTNOT, DMCONTROL_INTERRUPT, dram_write32(), dump_debug_ram(), ERROR_FAIL, ERROR_OK, get_info(), increase_dbus_busy_delay(), increase_interrupt_high_delay(), info, LOG_DEBUG, LOG_ERROR, LOG_INFO, scans_t::next_scan, scans_add_read32(), scans_add_write32(), scans_delete(), scans_execute(), scans_get_u32(), scans_new(), status, and wait_for_debugint_clear().
Referenced by examine(), execute_resume(), halt(), read_memory(), read_remote_csr(), register_read(), register_write(), riscv011_get_register(), setup_write_memory(), write_gpr(), write_memory(), and write_remote_csr().
◆ COMMAND_HELPER()
|
static |
Definition at line 2355 of file riscv-011.c.
References CMD, dbus_read(), DMINFO, DMINFO_AUTHENTICATED, and get_field().
◆ dbus_read()
|
static |
Definition at line 468 of file riscv-011.c.
References address, DBUS_OP_READ, dbus_scan(), DBUS_STATUS_BUSY, DBUS_STATUS_FAILED, DBUS_STATUS_SUCCESS, increase_dbus_busy_delay(), LOG_ERROR, and status.
Referenced by COMMAND_HELPER(), dram_check32(), dram_read32(), examine(), riscv011_authdata_read(), and wait_for_authbusy().
◆ dbus_scan()
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Definition at line 420 of file riscv-011.c.
References buf_get_u32(), buf_get_u64(), buf_set_u64(), DBUS_ADDRESS_START, DBUS_DATA_SIZE, DBUS_DATA_START, DBUS_OP_SIZE, DBUS_OP_START, DBUS_STATUS_FAILED, dump_field(), ERROR_OK, get_info(), info, jtag_add_dr_scan(), jtag_add_runtest(), jtag_execute_queue(), LOG_ERROR, LOG_TARGET_ERROR, scan_field::num_bits, op, target::tap, and TAP_IDLE.
Referenced by dbus_read(), dbus_write(), and read_bits().
◆ dbus_write()
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Definition at line 497 of file riscv-011.c.
References address, DBUS_OP_WRITE, dbus_scan(), DBUS_STATUS_BUSY, DBUS_STATUS_SUCCESS, increase_dbus_busy_delay(), LOG_ERROR, NULL, and status.
Referenced by cache_write(), dram_write32(), execute_resume(), and riscv011_authdata_write().
◆ deassert_reset()
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Definition at line 2006 of file riscv-011.c.
References jtag_add_ir_scan(), target::reset_halt, select_dbus, target::tap, TAP_IDLE, TARGET_HALTED, TARGET_RUNNING, and wait_for_state().
◆ deinit_target()
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Definition at line 1433 of file riscv-011.c.
References target::arch_info, info, LOG_DEBUG, and NULL.
◆ dram_address()
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Definition at line 301 of file riscv-011.c.
Referenced by dram_check32(), dram_read32(), dram_write32(), and execute_resume().
◆ dram_check32()
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Definition at line 753 of file riscv-011.c.
References address, dbus_read(), dram_address(), ERROR_FAIL, ERROR_OK, and LOG_ERROR.
Referenced by cache_check().
◆ dram_read32()
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Definition at line 674 of file riscv-011.c.
References address, dbus_read(), and dram_address().
Referenced by cache_get32(), and dump_debug_ram().
◆ dram_write32()
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Definition at line 681 of file riscv-011.c.
References dbus_write(), DMCONTROL_HALTNOT, DMCONTROL_INTERRUPT, and dram_address().
Referenced by assert_reset(), cache_write(), dram_write_jump(), and execute_resume().
◆ dram_write_jump()
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Definition at line 1015 of file riscv-011.c.
References DEBUG_RAM_START, DEBUG_ROM_RESUME, dram_write32(), jal(), and MAX_INT21.
Referenced by assert_reset(), and execute_resume().
◆ dump_debug_ram()
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Definition at line 812 of file riscv-011.c.
References DRAM_CACHE_SIZE, dram_read32(), and LOG_ERROR.
Referenced by cache_check(), cache_write(), and examine().
◆ dump_field()
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Definition at line 389 of file riscv-011.c.
References buf_get_u64(), DBUS_ADDRESS_START, DBUS_DATA_START, DBUS_OP_SIZE, DBUS_OP_START, DMCONTROL_HALTNOT, DMCONTROL_INTERRUPT, scan_field::in_value, LOG_LEVEL_IS, LOG_LVL_DEBUG, log_printf_lf(), scan_field::num_bits, and scan_field::out_value.
Referenced by dbus_scan(), and scans_dump().
◆ examine()
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Definition at line 1493 of file riscv-011.c.
References cache_check(), cache_get32(), cache_invalidate(), cache_set32(), cache_set_jump(), cache_write(), CSR_MISA, dbus_read(), DEBUG_RAM_START, DMINFO, DMINFO_ABUSSIZE, DMINFO_ACCESS128, DMINFO_ACCESS16, DMINFO_ACCESS32, DMINFO_ACCESS64, DMINFO_ACCESS8, DMINFO_AUTHBUSY, DMINFO_AUTHENTICATED, DMINFO_AUTHTYPE, DMINFO_DRAMSIZE, DMINFO_SERIALCOUNT, DMINFO_VERSION, DTMCONTROL_ADDRBITS, DTMCONTROL_IDLE, DTMCONTROL_VERSION, dtmcs_scan(), dump_debug_ram(), ERROR_FAIL, ERROR_OK, get_field(), get_field32(), get_info(), idcode_scan(), info, LOG_DEBUG, LOG_ERROR, LOG_INFO, LOG_WARNING, read_remote_csr(), riscv011_poll(), riscv011_reg_init_all(), riscv_info(), RISCV_INFO, riscv_xlen(), S1, srli(), sw(), target::tap, target_set_examined(), riscv_info::xlen, xori(), and ZERO.
◆ execute_resume()
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Definition at line 1123 of file riscv-011.c.
References buf_get_u64(), cache_invalidate(), cache_set(), cache_set32(), cache_set_jump(), cache_set_load(), cache_write(), CSR_DCSR, CSR_DPC, CSR_MSTATUS, csrw(), dbus_write(), DCSR_HALT, DCSR_STEP, DEBUG_RAM_START, DMCONTROL_INTERRUPT, dram_address(), dram_write32(), dram_write_jump(), ERROR_FAIL, ERROR_OK, fence_i(), GDB_REGNO_MSTATUS, get_info(), info, LOG_DEBUG, LOG_ERROR, lw(), maybe_write_tselect(), target::reg_cache, reg_cache::reg_list, riscv_reg_cache_invalidate_all(), riscv_reg_flush_all(), riscv_xlen(), S0, set_ebreakx_fields(), SLOT0, target::state, step(), TARGET_RUNNING, reg::valid, reg::value, wait_for_debugint_clear(), and ZERO.
Referenced by full_step(), and riscv011_resume().
◆ full_step()
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Definition at line 1187 of file riscv-011.c.
References ERROR_FAIL, ERROR_OK, execute_resume(), handle_halt(), LOG_ERROR, NULL, poll_target(), riscv_get_command_timeout_sec(), start, target::state, and TARGET_DEBUG_RUNNING.
Referenced by step(), and strict_step().
◆ get_info()
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Definition at line 221 of file riscv-011.c.
References target::arch_info, and info.
Referenced by add_dbus_scan(), assert_reset(), cache_check(), cache_clean(), cache_get32(), cache_invalidate(), cache_set32(), cache_write(), dbus_scan(), examine(), execute_resume(), handle_halt(), handle_halt_routine(), increase_dbus_busy_delay(), increase_interrupt_high_delay(), maybe_read_tselect(), maybe_write_tselect(), read_bits(), read_memory(), read_remote_csr(), register_read(), register_write(), riscv011_get_register(), slot_offset(), and write_memory().
◆ halt()
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Definition at line 1415 of file riscv-011.c.
References cache_set32(), cache_set_jump(), cache_write(), CSR_DCSR, CSR_MHARTID, csrr(), csrsi(), DCSR_HALT, ERROR_FAIL, ERROR_OK, jtag_add_ir_scan(), LOG_DEBUG, LOG_ERROR, S0, select_dbus, SETHALTNOT, sw(), target::tap, TAP_IDLE, and ZERO.
◆ handle_halt()
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Since almost everything can be accomplish by scanning the dbus register, all functions here assume dbus is already selected.
The exception are functions called directly by OpenOCD, which can't assume anything about what's currently in IR. They should set IR to dbus explicitly. Code structure
At the bottom of the stack are the OpenOCD JTAG functions: jtag_add_[id]r_scan jtag_execute_query jtag_add_runtest
There are a few functions to just instantly shift a register and get its value: dtmcontrol_scan idcode_scan dbus_scan
Because doing one scan and waiting for the result is slow, most functions batch up a bunch of dbus writes and then execute them all at once. They use the scans "class" for this: scans_new scans_delete scans_execute scans_add_... Usually you new(), call a bunch of add functions, then execute() and look at the results by calling scans_get...()
Optimized functions will directly use the scans class above, but slightly lazier code will use the cache functions that in turn use the scans functions: cache_get... cache_set... cache_write cache_set... update a local structure, which is then synced to the target with cache_write(). Only Debug RAM words that are actually changed are sent to the target. Afterwards use cache_get... to read results.
Definition at line 1853 of file riscv-011.c.
References DBG_REASON_BREAKPOINT, DBG_REASON_DBGRQ, DBG_REASON_SINGLESTEP, DBG_REASON_WATCHPOINT, DCSR_CAUSE, DCSR_CAUSE_DEBUGINT, DCSR_CAUSE_HALT, DCSR_CAUSE_HWBP, DCSR_CAUSE_STEP, DCSR_CAUSE_SWBP, target::debug_reason, ERROR_FAIL, ERROR_OK, get_field(), get_info(), handle_halt_routine(), info, LOG_ERROR, LOG_USER, maybe_read_tselect(), RE_AGAIN, RE_OK, riscv_enumerate_triggers(), riscv_semihosting(), SEMIHOSTING_NONE, target::state, target_call_event_callbacks(), TARGET_EVENT_HALTED, TARGET_HALTED, and target_was_examined().
Referenced by full_step(), and poll_target().
◆ handle_halt_routine()
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Definition at line 1625 of file riscv-011.c.
References address, ARRAY_SIZE, cache_invalidate(), csr, CSR_DCSR, CSR_DPC, CSR_DSCRATCH0, csrr(), DBUS_ADDRESS_START, DBUS_DATA_SIZE, DBUS_DATA_START, DBUS_OP_SIZE, DBUS_OP_START, DBUS_STATUS_BUSY, DBUS_STATUS_FAILED, DBUS_STATUS_SUCCESS, DMCONTROL_INTERRUPT, ERROR_OK, GDB_REGNO_DCSR, GDB_REGNO_DPC, get_info(), increase_dbus_busy_delay(), increase_interrupt_high_delay(), info, LOG_ERROR, scans_t::next_scan, RE_AGAIN, RE_FAIL, RE_OK, reg_cache_get(), reg_cache_set(), riscv_xlen(), S0, S1, scans_add_read(), scans_add_read32(), scans_add_write32(), scans_add_write_jump(), scans_add_write_load(), scans_add_write_store(), scans_delete(), scans_execute(), scans_get_u32(), scans_get_u64(), scans_new(), SLOT0, SLOT_LAST, and status.
Referenced by handle_halt().
◆ idcode_scan()
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Definition at line 309 of file riscv-011.c.
References buf_get_u32(), ERROR_OK, scan_field::in_value, jtag_add_dr_scan(), jtag_add_ir_scan(), jtag_execute_queue(), LOG_DEBUG, LOG_ERROR, NULL, scan_field::num_bits, scan_field::out_value, select_dbus, select_idcode, target::tap, and TAP_IDLE.
Referenced by examine().
◆ increase_dbus_busy_delay()
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Definition at line 336 of file riscv-011.c.
References DTMCONTROL_DBUS_RESET, dtmcs_scan(), get_info(), info, LOG_DEBUG, NULL, and target::tap.
Referenced by cache_write(), dbus_read(), dbus_write(), handle_halt_routine(), read_bits(), read_memory(), and write_memory().
◆ increase_interrupt_high_delay()
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Definition at line 347 of file riscv-011.c.
References get_info(), info, and LOG_DEBUG.
Referenced by cache_write(), handle_halt_routine(), read_memory(), and write_memory().
◆ init_target()
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Definition at line 2436 of file riscv-011.c.
References access_memory(), ERROR_FAIL, ERROR_OK, LOG_DEBUG, riscv011_authdata_read(), riscv011_authdata_write(), riscv011_get_impebreak(), riscv011_get_progbufsize(), riscv011_reg_init_all(), and RISCV_INFO.
◆ load()
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Definition at line 259 of file riscv-011.c.
References ld(), lw(), offset, and riscv_xlen().
Referenced by cache_set_load(), and load_slot().
◆ load_slot()
Definition at line 285 of file riscv-011.c.
References DEBUG_RAM_START, load(), MAX_INT12, offset, slot_offset(), and ZERO.
Referenced by scans_add_write_load().
◆ maybe_read_tselect()
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Definition at line 1085 of file riscv-011.c.
References CSR_TSELECT, ERROR_OK, get_info(), info, and read_remote_csr().
Referenced by handle_halt().
◆ maybe_write_tselect()
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Definition at line 1099 of file riscv-011.c.
References CSR_TSELECT, ERROR_OK, get_info(), info, and write_remote_csr().
Referenced by execute_resume(), register_write(), and riscv011_get_register().
◆ poll_target()
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Definition at line 1930 of file riscv-011.c.
References bits, ERROR_FAIL, ERROR_OK, handle_halt(), jtag_add_ir_scan(), LOG_DEBUG, read_bits(), select_dbus, target::state, target::tap, TAP_IDLE, TARGET_DEBUG_RUNNING, TARGET_HALTED, and TARGET_RUNNING.
Referenced by full_step(), and riscv011_poll().
◆ read_bits()
Read the haltnot and interrupt bits.
Definition at line 691 of file riscv-011.c.
References DBUS_DATA_SIZE, DBUS_OP_READ, dbus_scan(), DBUS_STATUS_BUSY, DBUS_STATUS_SUCCESS, DMCONTROL, DMCONTROL_HALTNOT, DMCONTROL_INTERRUPT, ERROR_FAIL, ERROR_OK, get_field(), get_info(), bits_t::haltnot, increase_dbus_busy_delay(), info, bits_t::interrupt, LOG_ERROR, and status.
Referenced by poll_target(), and wait_for_debugint_clear().
◆ read_memory()
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Definition at line 2015 of file riscv-011.c.
References address, riscv_mem_access_args::address, buffer, cache_clean(), CACHE_NO_READ, cache_set32(), cache_set_jump(), cache_write(), count, riscv_mem_access_args::count, DBUS_DATA_SIZE, DBUS_DATA_START, DBUS_OP_SIZE, DBUS_OP_START, DBUS_STATUS_BUSY, DBUS_STATUS_FAILED, DBUS_STATUS_SUCCESS, DEBUG_RAM_START, DMCONTROL_INTERRUPT, ERROR_FAIL, ERROR_NOT_IMPLEMENTED, ERROR_OK, get_info(), increase_dbus_busy_delay(), increase_interrupt_high_delay(), riscv_mem_access_args::increment, info, jtag_add_ir_scan(), lb(), lh(), LOG_DEBUG, LOG_ERROR, LOG_INFO, LOG_USER, lw(), MIN, offset, riscv_mem_access_args::read_buffer, riscv_mem_access_is_read(), S0, S1, scans_add_read32(), scans_add_write32(), scans_delete(), scans_execute(), scans_get_u32(), scans_get_u64(), scans_new(), scans_reset(), select_dbus, size, riscv_mem_access_args::size, status, sw(), target::tap, TAP_IDLE, TARGET_PRIxADDR, wait_for_debugint_clear(), and ZERO.
Referenced by access_memory().
◆ read_remote_csr()
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Definition at line 1040 of file riscv-011.c.
References cache_get(), cache_get32(), cache_set32(), cache_set_jump(), cache_set_store(), cache_write(), csr, csrr(), ERROR_FAIL, ERROR_OK, GDB_REGNO_CSR0, get_info(), info, LOG_DEBUG, LOG_WARNING, riscv_reg_gdb_regno_name(), S0, and SLOT0.
Referenced by examine(), and maybe_read_tselect().
◆ reg_cache_get()
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Definition at line 1208 of file riscv-011.c.
References buf_get_u64(), LOG_DEBUG, LOG_ERROR, reg::name, number, target::reg_cache, reg_cache::reg_list, reg::size, reg::valid, and reg::value.
Referenced by handle_halt_routine(), and riscv011_get_register().
◆ reg_cache_set()
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Definition at line 1220 of file riscv-011.c.
References buf_set_u64(), LOG_DEBUG, reg::name, number, target::reg_cache, reg_cache::reg_list, reg::size, reg::valid, and reg::value.
Referenced by handle_halt_routine(), and riscv011_set_register().
◆ register_read()
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Definition at line 1245 of file riscv-011.c.
References cache_get(), cache_get32(), cache_set32(), cache_set_jump(), cache_set_store(), cache_write(), csrr(), ERROR_FAIL, ERROR_OK, GDB_REGNO_CSR0, GDB_REGNO_CSR4095, GDB_REGNO_MSTATUS, get_info(), info, LOG_DEBUG, LOG_ERROR, LOG_WARNING, riscv_reg_gdb_regno_name(), S0, SLOT0, and reg::value.
Referenced by riscv011_get_register().
◆ register_write()
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Definition at line 1277 of file riscv-011.c.
References cache_get32(), cache_set(), cache_set32(), cache_set_jump(), cache_set_load(), cache_set_store(), cache_write(), CSR_DSCRATCH0, CSR_MSTATUS, csrw(), DCSR_PRV, DEBUG_RAM_START, ERROR_FAIL, ERROR_OK, fld(), flw(), GDB_REGNO_CSR0, GDB_REGNO_CSR4095, GDB_REGNO_DPC, GDB_REGNO_FPR0, GDB_REGNO_FPR31, GDB_REGNO_MSTATUS, GDB_REGNO_PC, GDB_REGNO_PRIV, GDB_REGNO_XPR31, GDB_REGNO_ZERO, get_info(), info, LOG_ERROR, LOG_WARNING, maybe_write_tselect(), MSTATUS_FS, number, riscv_reg_gdb_regno_name(), riscv_xlen(), S0, S1, set_field(), SLOT0, SLOT1, SLOT_LAST, update_mstatus_actual(), and reg::value.
Referenced by riscv011_set_register(), step(), and write_memory().
◆ riscv011_authdata_read()
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Definition at line 2394 of file riscv-011.c.
References dbus_read(), DMAUTHDATA0, DMAUTHDATA1, ERROR_FAIL, ERROR_OK, LOG_ERROR, and wait_for_authbusy().
Referenced by init_target().
◆ riscv011_authdata_write()
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Definition at line 2410 of file riscv-011.c.
References dbus_write(), DMAUTHDATA0, DMAUTHDATA1, ERROR_FAIL, ERROR_OK, LOG_ERROR, and wait_for_authbusy().
Referenced by init_target().
◆ riscv011_get_impebreak()
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Definition at line 2426 of file riscv-011.c.
Referenced by init_target().
◆ riscv011_get_progbufsize()
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Definition at line 2431 of file riscv-011.c.
Referenced by init_target().
◆ riscv011_get_register()
| int riscv011_get_register | ( | struct target * | target, |
| riscv_reg_t * | value, | ||
| enum gdb_regno | regid | ||
| ) |
Definition at line 1344 of file riscv-011.c.
References cache_set(), cache_set32(), cache_set_jump(), cache_set_load(), cache_write(), CSR_MSTATUS, csrw(), DCSR_PRV, DEBUG_RAM_START, ERROR_FAIL, ERROR_OK, fsd(), fsw(), GDB_REGNO_DPC, GDB_REGNO_FPR0, GDB_REGNO_FPR31, GDB_REGNO_PC, GDB_REGNO_PRIV, GDB_REGNO_XPR31, get_field(), get_info(), info, maybe_write_tselect(), MSTATUS_FS, reg_cache_get(), register_read(), riscv_xlen(), S0, set_field(), SLOT1, update_mstatus_actual(), and reg::value.
Referenced by riscv011_reg_get(), riscv_reg_get(), and update_mstatus_actual().
◆ riscv011_poll()
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Definition at line 1957 of file riscv-011.c.
References poll_target().
Referenced by examine(), and wait_for_state().
◆ riscv011_resume()
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Definition at line 1962 of file riscv-011.c.
References execute_resume(), jtag_add_ir_scan(), RISCV_INFO, select_dbus, target::tap, and TAP_IDLE.
◆ riscv011_set_register()
| int riscv011_set_register | ( | struct target * | target, |
| enum gdb_regno | regid, | ||
| riscv_reg_t | value | ||
| ) |
Definition at line 1392 of file riscv-011.c.
References reg::dirty, ERROR_OK, GDB_REGNO_XPR31, target::reg_cache, reg_cache_set(), reg_cache::reg_list, register_write(), reg::valid, and reg::value.
Referenced by riscv011_reg_set(), and riscv_set_or_write_register().
◆ scans_add_read()
Add one or more scans to read the indicated slot.
Definition at line 646 of file riscv-011.c.
References riscv_xlen(), scans_add_read32(), slot_offset(), and scans_t::target.
Referenced by handle_halt_routine().
◆ scans_add_read32()
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Add a 32-bit dbus read.
Definition at line 634 of file riscv-011.c.
References add_dbus_scan(), address, DBUS_OP_READ, DMCONTROL_HALTNOT, DMCONTROL_INTERRUPT, scans_t::field, scans_t::in, scans_t::next_scan, scans_t::out, scans_t::scan_count, scans_t::scan_size, and scans_t::target.
Referenced by cache_write(), handle_halt_routine(), read_memory(), scans_add_read(), and write_memory().
◆ scans_add_write32()
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Add a 32-bit dbus write to the scans structure.
Definition at line 593 of file riscv-011.c.
References add_dbus_scan(), address, DBUS_OP_WRITE, DMCONTROL_HALTNOT, DMCONTROL_INTERRUPT, scans_t::field, scans_t::in, scans_t::next_scan, scans_t::out, scans_t::scan_count, scans_t::scan_size, and scans_t::target.
Referenced by cache_write(), handle_halt_routine(), read_memory(), scans_add_write_jump(), scans_add_write_load(), scans_add_write_store(), and write_memory().
◆ scans_add_write_jump()
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Add a 32-bit dbus write for an instruction that jumps to the beginning of debug RAM.
Definition at line 607 of file riscv-011.c.
References address, DEBUG_RAM_START, DEBUG_ROM_RESUME, jal(), MAX_INT21, and scans_add_write32().
Referenced by handle_halt_routine().
◆ scans_add_write_load()
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Add a 32-bit dbus write for an instruction that loads from the indicated slot.
Definition at line 617 of file riscv-011.c.
References address, load_slot(), scans_add_write32(), and scans_t::target.
Referenced by handle_halt_routine().
◆ scans_add_write_store()
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Add a 32-bit dbus write for an instruction that stores to the indicated slot.
Definition at line 626 of file riscv-011.c.
References address, scans_add_write32(), store_slot(), and scans_t::target.
Referenced by handle_halt_routine().
◆ scans_delete()
Definition at line 558 of file riscv-011.c.
References scans_t::field, scans_t::in, NULL, and scans_t::out.
Referenced by cache_write(), handle_halt_routine(), read_memory(), and write_memory().
◆ scans_dump()
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Definition at line 573 of file riscv-011.c.
References dump_field(), scans_t::field, and scans_t::next_scan.
Referenced by scans_execute().
◆ scans_execute()
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Definition at line 579 of file riscv-011.c.
References ERROR_OK, jtag_execute_queue(), LOG_ERROR, and scans_dump().
Referenced by cache_write(), handle_halt_routine(), read_memory(), and write_memory().
◆ scans_get_u32()
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Definition at line 660 of file riscv-011.c.
References buf_get_u32(), scans_t::in, and scans_t::scan_size.
Referenced by cache_write(), handle_halt_routine(), read_memory(), and write_memory().
◆ scans_get_u64()
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Definition at line 666 of file riscv-011.c.
References buf_get_u64(), scans_t::in, and scans_t::scan_size.
Referenced by handle_halt_routine(), and read_memory().
◆ scans_new()
Definition at line 524 of file riscv-011.c.
References scans_t::field, scans_t::in, scans_t::next_scan, NULL, scans_t::out, riscv_xlen(), scans_t::scan_count, scans_t::scan_size, target, and scans_t::target.
Referenced by cache_write(), handle_halt_routine(), read_memory(), and write_memory().
◆ scans_reset()
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Definition at line 568 of file riscv-011.c.
References scans_t::next_scan.
Referenced by read_memory(), and write_memory().
◆ set_ebreakx_fields()
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Definition at line 1113 of file riscv-011.c.
References config, DCSR_EBREAKH, DCSR_EBREAKM, DCSR_EBREAKS, DCSR_EBREAKU, RISCV_MODE_M, RISCV_MODE_S, RISCV_MODE_U, riscv_private_config(), and set_field().
Referenced by assert_reset(), and execute_resume().
◆ setup_write_memory()
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Definition at line 2166 of file riscv-011.c.
References addi(), cache_set32(), cache_set_jump(), cache_write(), DEBUG_RAM_START, ERROR_FAIL, ERROR_OK, lb(), lh(), LOG_ERROR, lw(), S0, sb(), sh(), size, sw(), T0, and ZERO.
Referenced by write_memory().
◆ slot_offset()
Definition at line 229 of file riscv-011.c.
References get_info(), info, LOG_ERROR, riscv_xlen(), SLOT0, SLOT1, and SLOT_LAST.
Referenced by cache_get(), cache_set(), cache_set_load(), cache_set_store(), load_slot(), scans_add_read(), and store_slot().
◆ step()
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Definition at line 1467 of file riscv-011.c.
References address, ERROR_OK, full_step(), GDB_REGNO_PC, jtag_add_ir_scan(), LOG_WARNING, register_write(), riscv_xlen(), select_dbus, strict_step(), target::tap, and TAP_IDLE.
Referenced by ch347_scratchpad_add_tms_change(), esirisc_resume_or_step(), execute_resume(), or1k_resume_or_step(), riscv013_on_step_or_resume(), riscv013_step_or_resume_current_hart(), and set_dcsr_ebreak().
◆ store()
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Definition at line 272 of file riscv-011.c.
References offset, riscv_xlen(), sd(), and sw().
Referenced by cache_set_store(), and store_slot().
◆ store_slot()
Definition at line 293 of file riscv-011.c.
References DEBUG_RAM_START, MAX_INT12, offset, slot_offset(), store(), and ZERO.
Referenced by scans_add_write_store().
◆ strict_step()
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Definition at line 1444 of file riscv-011.c.
References ERROR_OK, full_step(), LOG_DEBUG, watchpoint::next, riscv_add_watchpoint(), riscv_remove_watchpoint(), and target::watchpoints.
Referenced by step().
◆ update_mstatus_actual()
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Definition at line 1229 of file riscv-011.c.
References ERROR_OK, GDB_REGNO_MSTATUS, target::reg_cache, reg_cache::reg_list, riscv011_get_register(), and reg::valid.
Referenced by register_write(), and riscv011_get_register().
◆ wait_for_authbusy()
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static |
Definition at line 2375 of file riscv-011.c.
References dbus_read(), DMINFO, DMINFO_AUTHBUSY, ERROR_FAIL, ERROR_OK, get_field(), LOG_ERROR, NULL, riscv_get_command_timeout_sec(), and start.
Referenced by riscv011_authdata_read(), and riscv011_authdata_write().
◆ wait_for_debugint_clear()
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Definition at line 725 of file riscv-011.c.
References bits, ERROR_FAIL, ERROR_OK, LOG_ERROR, NULL, read_bits(), riscv_get_command_timeout_sec(), and start.
Referenced by assert_reset(), cache_write(), execute_resume(), read_memory(), and write_memory().
◆ wait_for_state()
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static |
Definition at line 1023 of file riscv-011.c.
References ERROR_FAIL, ERROR_OK, LOG_ERROR, NULL, riscv011_poll(), riscv_get_command_timeout_sec(), start, state, and target::state.
Referenced by deassert_reset().
◆ write_gpr()
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static |
Definition at line 1075 of file riscv-011.c.
References cache_set(), cache_set_jump(), cache_set_load(), cache_write(), ERROR_FAIL, ERROR_OK, and SLOT0.
Referenced by write_memory().
◆ write_memory()
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static |
Definition at line 2192 of file riscv-011.c.
References address, riscv_mem_access_args::address, buffer, cache_clean(), cache_get(), cache_set(), cache_set_jump(), cache_set_load(), cache_set_store(), cache_write(), count, riscv_mem_access_args::count, DBUS_DATA_START, DBUS_OP_SIZE, DBUS_OP_START, DBUS_STATUS_BUSY, DBUS_STATUS_FAILED, DBUS_STATUS_SUCCESS, ERROR_FAIL, ERROR_NOT_IMPLEMENTED, ERROR_OK, get_info(), increase_dbus_busy_delay(), increase_interrupt_high_delay(), riscv_mem_access_args::increment, info, jtag_add_ir_scan(), LOG_DEBUG, LOG_ERROR, LOG_INFO, LOG_TARGET_ERROR, MIN, offset, register_write(), riscv_mem_access_is_write(), scans_add_read32(), scans_add_write32(), scans_delete(), scans_execute(), scans_get_u32(), scans_new(), scans_reset(), select_dbus, setup_write_memory(), size, riscv_mem_access_args::size, SLOT0, SLOT1, status, T0, t0, target::tap, TAP_IDLE, TARGET_PRIxADDR, wait_for_debugint_clear(), riscv_mem_access_args::write_buffer, and write_gpr().
Referenced by access_memory().
◆ write_remote_csr()
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Definition at line 1062 of file riscv-011.c.
References cache_set(), cache_set32(), cache_set_jump(), cache_set_load(), cache_write(), csr, csrw(), ERROR_FAIL, ERROR_OK, LOG_DEBUG, S0, and SLOT0.
Referenced by maybe_write_tselect().
Variable Documentation
◆ riscv011_target
| struct target_type riscv011_target |
Definition at line 2436 of file riscv-011.c.
Referenced by get_target_type().
